Thesis Specification
Introduction
The thesis is about the implementation of a DDR SDRAM Memory Controller that supports the AMBA AHB interface.
Goal
The goals for the project are:
- To evaluate the possibilites and problems involved with designing and implementing a DDR SDRAM Memory Controller
Timeplan
Date | Milestone | Status |
2002-09-06 | Introduction and reading the JEDEC specifications | Done |
2002-09-13 | Design and implementation the memory controller | Done |
2002-09-20 | Working simulation of the memory controller | Done |
2002-10-04 | Design and implementation of the AHB interface | Done |
2002-10-11 | Working simulation of the AHB interface | Done |
2002-10-25 | Setting up and running a simulation with an ARM9 CPU | Canceled |
2002-11-15 | Synthesis and backannoted simulation of netlist | Done |
2002-12-06 | Place and rout with Apollo and simulation of netlist | Done |
2002-12-13 | Evaluations and Improvments | Done |
2002-01-17 | Writing the final report | Done |
2002-01-24 | Oral presentation | Done |
Time Report
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Documents
Links
- JEDEC Solid State Technology Association
- AMBA On-Chip Bus
- Collins, Nikel DDR-SDRAM high-speed, source-synchronous interfaces create deisgn callenges
- Elpida How to use DDR SDRAM
- Vollrath Characterizing SDRAMS
- Konishi, Iwamoto, Sawada, Muria, Araki, Kumanoya Dual Clock Scheme for over 200 MHz Synchronous DRAM System
- Samsung Electronics Key points for controller design
- Lines, Abou-Seido, Mar, Achyuthan, Miyamoto, Murashima, Sakuma High Speed Circuit Techniques in a 150 MHz 64M SDRAM
- Davis, Jacobe, Mudge The new DRAM Interfaces: SDRAM, RDRAM and Variants